There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells.
NOR Array
In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. One typical memory cell has a “split-channel” between source and drain diffusions. A charge storage element of the cell is positioned over one portion of the channel and the word line (also referred to as a control gate) is positioned over the other channel portion as well as over the charge storage element. This effectively forms a cell with two transistors in series, one (the memory transistor) with a combination of the amount of charge on the charge storage element and the voltage on the word line controlling the amount of current that can flow through its portion of the channel, and the other (the select transistor) having the word line alone serving as its gate. The word line extends over a row of charge storage elements. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, and in co-pending U.S. patent application Ser. No. 09/239,073, filed Jan. 27, 1999, now U.S. Pat No. 6,281,075.
A modification of this split-channel flash EEPROM cell adds a steering gate positioned between the charge storage element and the word line. Each steering gate of an array extends over one column of charge storage elements, perpendicular to the word line. The effect is to relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the charge storage element to a desired level through an electric field (capacitive) coupling between the word line and the charge storage element. It is often difficult to perform both of these functions in an optimum manner with a single voltage. With the addition of the steering gate, the word line need only perform function (1), while the added steering gate performs function (2). The use of steering gates in a flash EEPROM array is described, for example, in U.S. Pat. Nos. 5,313,421 and 6,222,762.
There are various programming techniques for injecting electrons from the substrate onto a floating gate storage element through the gate dielectric. The most common programming mechanisms are described in a book edited by Brown and Brewer, Nonvolatile Semiconductor Memory Technology, IEEE Press, section 1.2, pages 9-25 (1998). One technique, termed channel “hot-electron injection” (section 1.2.3), injects electrons from the cell's channel into a region of the floating gate adjacent the cell's drain. Another technique, termed “source side injection” (section 1.2.4), controls the substrate surface electrical potential along the length of the memory cell channel in a manner to create conditions for electron injection in a region of the channel away from the drain. Source side injection is also described in an article by Kamiya et al., “EPROM Cell with High Gate Injection Efficiency,” IEDM Technical Digest, 1982, pages 741-744, and in U.S. Pat. Nos. 4,622,656 and 5,313,421.
Two techniques for removing charge from charge storage elements to erase memory cells are used in both of the two types of NOR memory cell arrays described above. One is to erase to the substrate by applying appropriate voltages to the source, drain and other gate(s) that cause electrons to tunnel through a portion of a dielectric layer between the storage element and the substrate. The other erase technique is to transfer electrons from the storage element to another gate through a tunnel dielectric layer positioned between them. In the first type of cell described above, a third erase gate is provided for that purpose. In the second type of cell described above, which already has three gates because of the use of a steering gate, the charge storage element is erased to the word line, without the necessity to add a fourth gate. Although this later technique adds back a second function to be performed by the word line, these functions are performed at different times, thus avoiding the necessity of making a compromise because of the two functions. When either erase technique is utilized, a large number of memory cells are grouped together for simultaneously erasure, in a “flash.” In one approach, the group includes enough memory cells to store the amount of user data stored in a disk sector, namely 512 bytes, plus some overhead data. In another approach, each group contains enough cells to hold several thousand bytes of user data, equal to many disk sectors' worth of data. Multi-block erasure, defect management and other flash EEPROM system features are described in U.S. Pat. No. 5,297,148.
As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM systems. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per cell, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338.
Another type of memory cell includes two storage elements that may also be operated in multiple states on each storage element. In this type of cell, two storage elements are included over its channel between source and drain diffusions with a select transistor in between them. A steering gate is included along each column of storage elements and a word line is provided thereover along each row of storage elements. When accessing a given storage element for reading or programming, the steering gate over the other storage element of the cell containing the storage element of interest is raised sufficiently high to turn on the channel under the other storage element no matter what charge level exists on it. This effectively eliminates the other storage element as a factor in reading or programming the storage element of interest in the same memory cell. For example, the amount of current flowing through the cell, which can be used to read its state, is then a function of the amount of charge on the storage element of interest but not of the other storage element in the same cell. Examples of this cell array architecture and operating techniques are described in U.S. Pat. Nos. 5,712,180, 6,103,573 and 6,151,248.
NAND Array
Another flash EEPROM architecture utilizes a NAND array, wherein series strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. An example of a NAND architecture array and its operation as part of a memory system is found in U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935.
Charge Storage Elements
The charge storage elements of current flash EEPROM arrays and discussed in the foregoing referenced patents and articles are most commonly electrically conductive floating gates, typically formed from doped polysilicon material. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.
U.S. Pat. No. 5,851,881 describes the use of two storage elements positioned adjacent each other over the channel of the memory cell, one being such a dielectric element and the other a conductive floating gate. Two bits of data are stored, one in the dielectric element and the other in the floating gate. The memory cell is programmed into one of four different threshold level combinations, representing one of four storage states, by programming each of the two gates into one of two different charge level ranges.
Another approach to storing two bits in each cell utilizing a dielectric storage element has been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading binary states of the spatially separated charge storage regions within the dielectric.
Large Erase Blocks
Memory cells of a typical non-volatile flash array are divided into discrete blocks of cells that are erased together. That is, the block is the erase unit. Each block typically stores one or more pages of data, the page being the unit of programming and reading, although more than one page may be programmed or read in a single operation. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example is a sector of 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which it is stored.
Block Experience Counts
The number of erase and re-programming cycles experienced by the individual blocks of memory cells are often maintained as part of optimizing control of the operation of the memory system. One reason to do so is because of a limited number of erase/writing cycles that flash EEPROM cells can endure. Performance and reliability are usually degraded as the number of such cycles increases, and the amount of such degradation that can be tolerated depends upon various operating parameters of the system. Some memory cell blocks are typically cycled more often than others in normal operation. When the cycle count of a block reaches a pre-set limit of expected endurance, that block can be mapped out of the system in favor of a redundant block. An example of this is described in U.S. Pat. No. 5,268,870, wherein the experience count of each block is stored as part of the overhead data within the block. U.S. Pat. No. 6,426,893 describes a system that stores the block experience counts, as well as other overhead data, in blocks separate from the blocks to which they pertain. Further, the experience count can be used to even the usage (wear) of the memory cell blocks of a system. The relative block experience counts are monitored by the system controller and, in response to a predetermined unevenness of use being detected, changing the logical-to-physical address conversion of blocks in order to direct future high volume re-writes to blocks with lower experience cycle counts. Examples of such wear leveling techniques are given in U.S. Pat. No. 6,081,447. As an alternative to maintaining the experience counts in the blocks to which they pertain, they may be stored in other blocks provided for block overhead information. An example of this is described in U.S. patent application Ser. No. 09/505,555, filed Feb. 17, 2000, now U.S. Pat. No. 6,426,893. In addition to using the experience count for purposes of block substitution, the count can also be used by the controller to set voltages used during programming, reading and/or erase operations, since the optimum voltages will often increase as usage increases.
The patents, patent applications, articles and book portions identified above are all hereby expressly incorporated in their entirety into this Background by these references.